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Publications of SPCL
|RDMA, Scalable MPI-3 RMA, and Next-Generation Post-RDMA Interconnects|
(Presentation - Apr. 2019)
Best talk award winner at Swiss HPC Advisory Council Conference 2019
AbstractModern interconnects offer remote direct memory access (RDMA) features. Yet, most applications rely on explicit message passing for communications albeit their unwanted overheads. The MPI-3.0 standard defines a programming interface for exploiting RDMA networks directly. We demonstrate how to efficiently implement the specification on modern RDMA networks. Our protocols support scaling to millions of cores with negligible memory consumption while providing highest performance and minimal overheads, comparable to, or better than UPC and CAF in terms of latency, bandwidth, and message rate. After this, we recognize that network cards contain rather powerful processors optimized for data movement and limiting the functionality to remote direct memory access seems unnecessarily constraining. We develop sPIN, a portable programming model to offload simple packet processing functions to the network card. To demonstrate the potential of the model, we design a cycle-accurate simulation environment by combining the network simulator LogGOPSim and the CPU simulator gem5. We implement offloaded message matching, datatype processing, and collective communications and demonstrate transparent full-application speedups. Furthermore, we show how sPIN can be used to accelerate redundant in-memory filesystems and several other use cases. Our work investigates a portable packet-processing network acceleration model similar to compute acceleration with CUDA or OpenCL. We show how such network acceleration enables an eco-system that can significantly speed up applications and system services.